The invention disclosed relates generally to ferroelectric transistors, and more particularly to a method for extending the data retention of ferroelectric transistors.
Ferroelectric transistors are structurally identical to metal-oxide-silicon field effect transistor (MOSFET) devices with the gate oxide layer replaced by a ferroelectric material layer 12, as shown in FIG. 1. The polarization state of the ferroelectric material layer 12 gives rise to an electric field, which shifts the turn-on threshold voltage of the device 10. Transistors known in the prior art often include a non-ferroelectric dielectric layer 16 between the ferroelectric material and the silicon substrate 18, as shown in the device 14 of FIG. 2. This dielectric layer 16 generally has several purposes at the silicon/ferroelectric interface including avoidance of uncontrolled growth of silicon dioxide, avoidance of high electric fields at the interface, separating the ferroelectric materials from the silicon, avoidance of crystal lattice structure mismatch between the silicon and the ferroelectric materials, and keeping hydrogen away from the ferroelectric materials. Such a dielectric layer 16 is sometimes also placed between the top electrode layer 20 and the ferroelectric layer 12 for the same reasons. These devices, such as devices 10 and 14 and variants thereof, are utilized in arrays of rows and columns to form one-transistor (xe2x80x9c1Txe2x80x9d) non-volatile ferroelectric memories.
When a voltage greater than a coercive voltage is applied across the ferroelectric material, the ferroelectric material polarizes in the direction aligning with the electric field. When the applied voltage is removed, the polarization state is preserved. When a voltage greater than the coercive voltage is applied to the ferroelectric material in the opposite direction, the polarization in the ferroelectric material reverses. When that electric field is removed, the reversed polarization state remains in the material. The electric field generated by the polarization offsets the natural tun-on threshold of the transistors, effectively shifting the turn-on thresholds of the transistors. By applying known voltages less than the coercive voltage on the terminals of the transistor, the state of the polarization within the ferroelectric material can be detected without altering the stored polarization states, a method known in the prior art as non-destructive read-out.
Though exhibiting many favorable properties such as small feature size, good endurance, and low read and write operating voltages, conventional ferroelectric transistors are known in the prior art to have poor retention time. The electric field generated by the polarization is reduced due to a number of factors including a depolarization field that reverses the polarization over time and compensation by impurities within the ferroelectric material. As the electric field is compensated, the threshold of the device shift is reduced until the sensing circuits can no longer detect the stored polarization state. The ferroelectric transistor has thereby lost the stored logic state.
Another type of non-volatile memory known in the prior art operates by injecting holes or electrons into a thin film, thereby shifting the turn-on threshold negatively or positively. Such memories include flash and non-volatile memories based on silicon nitride thin films. Electrons or holes are injected into a thin film by applying a voltage significantly larger than the read operating voltage. Such memories are known to exhibit excellent retention characteristics, but have marginal endurance properties, slow write times, and high power consumption during write cycles. What is desired, therefore, is a non-volatile ferroelectric device that exhibits the desirable retention characteristics of a flash memory but without the undesirable properties of low endurance, slow write times, and high power consumption.
According to principles of the present invention, a novel apparatus and method extends data retention of a ferroelectric transistor exhibiting hysteresis by injecting holes or electrons into the ferroelectric transistor when power is removed. The ferroelectric FET has a mechanism to trap charge in a buffer dielectric layer or in the ferroelectric layer sandwiched between a top electrode and the silicon substrate. The state of polarization is detected before power is removed from the ferroelectric FET. Charge is injected into the ferroelectric FET to produce a first threshold voltage when a first polarization state is determined before power is removed. Charge is removed from the ferroelectric FET to produce a second threshold voltage when a second polarization state is determined before power is removed. When the ferroelectric FET is powered up again, the charge state is determined. The ferroelectric FET is then polarized to correspond to a first threshold voltage when the charge state corresponding to the first threshold is determined. The ferroelectric FET is polarized to correspond to a second threshold voltage when a charge state corresponding to the second threshold is determined. Charge mechanisms include tunneling mechanisms. Fowler Nordheim tunneling, avalanche breakdown, hot carrier injection, and impact ionization. In one embodiment, charge is injected only into the drain region of the ferroelectric FET, the FET being operated so that injected charge is determined by passing current through the ferroelectric FET with source and drain reversed, a high current representing a first charge state corresponding to a first threshold and a lower current representing a second charge state corresponding to a second threshold. In another embodiment, a sense amplifier is utilized that can operate around a first operating point and a second operating point induced by the injected charge, while differentiating a first polarization state and a second polarization state around first operating point and second operating point.
The foregoing and other objects, features and advantages of the invention will become more readily apparent from the following detailed description of a preferred embodiment of the invention, which proceeds with reference to the accompanying drawings.